Reconfigurable FPGA-Based Acceleration of RTL Simulation and Co-Simulation for Cloud Datacenter Workloads

Abstract

The complexities that have arisen in the form of increasing workloads in cloud datacenters are further complicating the efficient Register Transfer Level (RTL) simulation and hardware/software co-simulation of high-performance computing platform design and verification. Traditional software-based RTL simulation can experience long response times and high computation time and are limited in scalability when performing an analysis of processor, accelerator, memory, and interconnect architecture on realistic workloads in datacenters. The paper provides a scaling FPGA-based accelerator model to leverage the performance of RTL simulation and co-simulation, through the utilization of hardware to run computationally intensive aspects of the simulation. The suggested model dynamically deploys the chosen RTL simulation kernels to FPGA resources as well as keeps in sync with a software simulation environment. A configurable communication and synchronization interface enables communication between host based simulators and FPGA accelerated modules and enables flexible workload and rapid architecture exploration. The framework is suited in the case of cloud datacenter with heterogeneous processors, accelerators, hierarchies in memory as well as high speed interconnection. Performance with respect to the simulation execution time, ratio of acceleration, and utilization of FPGA resources, overhead of synchronization and scalability across workload settings are measured. The gradually increasing reduction of simulation latency with modeling accuracy and rapid validation of hardware-software design can be approached using the suggested approach that provides a scalable foundation.