Reconfigurable FPGA-Based Acceleration of RTL Simulation and Co-Simulation for Cloud Datacenter Workloads
Main Article Content
Abstract
The complexities that have arisen in the form of increasing workloads in cloud datacenters are further complicating the efficient Register Transfer Level (RTL) simulation and hardware/software co-simulation of high-performance computing platform design and verification. Traditional software-based RTL simulation can experience long response times and high computation time and are limited in scalability when performing an analysis of processor, accelerator, memory, and interconnect architecture on realistic workloads in datacenters. The paper provides a scaling FPGA-based accelerator model to leverage the performance of RTL simulation and co-simulation, through the utilization of hardware to run computationally intensive aspects of the simulation. The suggested model dynamically deploys the chosen RTL simulation kernels to FPGA resources as well as keeps in sync with a software simulation environment. A configurable communication and synchronization interface enables communication between host based simulators and FPGA accelerated modules and enables flexible workload and rapid architecture exploration. The framework is suited in the case of cloud datacenter with heterogeneous processors, accelerators, hierarchies in memory as well as high speed interconnection. Performance with respect to the simulation execution time, ratio of acceleration, and utilization of FPGA resources, overhead of synchronization and scalability across workload settings are measured. The gradually increasing reduction of simulation latency with modeling accuracy and rapid validation of hardware-software design can be approached using the suggested approach that provides a scalable foundation.
Article Details
Section
How to Cite
References
[4] Elsabbagh, F., Sheikhha, S., Ying, V. A., Nguyen, Q. M., Emer, J. S., & Sánchez, D. (2023). Accelerating RTL simulation with hardware-software co-design. In Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 153–166). Association for Computing Machinery. https://doi.org/10.1145/3613424.3614257
[5] Wang, H., & Beamer, S. (2023). RepCut: Superlinear parallel RTL simulation with replication-aided partitioning. In Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (Vol. 2, pp. 219–232). Association for Computing Machinery. https://doi.org/10.1145/3582016.3582034
[6] Zhou, K., Liang, Y., Lin, Y., Wang, R., & Huang, R. (2023). Khronos: Fusing memory access for improved hardware RTL simulation. In Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 411–424). Association for Computing Machinery. https://doi.org/10.1145/3613424.3614275
[7] López-Paradís, G., Li, B., Armejach, A., Wallentowitz, S., & Moretó, M. (2023). Fast behavioural RTL simulation of 10B transistor SoC designs with Metro-MPI. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1–6). IEEE. https://doi.org/10.23919/DATE56975.2023.10137080
[8] Lin, D.-L., Ren, H., Zhang, Y., Khailany, B., & Huang, T.-W. (2022). From RTL to CUDA: A GPU acceleration flow for RTL simulation with batch stimulus. In Proceedings of the 51st International Conference on Parallel Processing (Article 91, pp. 1–11). Association for Computing Machinery. https://doi.org/10.1145/3545008.3545091
[9] Chatterjee, D., DeOrio, A., & Bertacco, V. (2011). Gate-level simulation with GPU computing. ACM Transactions on Design Automation of Electronic Systems, 16(3), Article 30. https://doi.org/10.1145/1970353.1970363
[10] Babb, J., Tessier, R., Dahl, M., Hanono, S., Hoki, D. M., & Agarwal, A. (1997). Logic emulation with virtual wires. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16(6), 609–626. https://doi.org/10.1109/43.640619
[11] Ahmad, T. B., Kim, N., Min, B., Kalia, A., Ciesielski, M., & Yang, S. (2012). Scalable parallel event-driven HDL simulation for multi-cores. In 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (pp. 205–208). IEEE. https://doi.org/10.1109/SMACD.2012.6339456
[12] Qian, H., & Deng, Y. (2011). Accelerating RTL simulation with GPUs. In Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design (pp. 752–757). IEEE. https://doi.org/10.1145/2051118.2051187
International Journal of Humanities and Information Technology (IJHIT)
e-ISSN: 2456 –1142, Volume 5, Issue 1, (March 2023), ijhit.info
March 2023 www.ijhit.info 118 | Page
[13] Nanjundappa, M., Patel, H. D., Jose, B. A., & Shukla, S. K. (2010). SCGPSim: A fast SystemC simulator on GPUs. In Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010) (pp. 145–150). IEEE. https://doi.org/10.1109/ASPDAC.2010.5419903
[14] Miller, J. E., Kasture, H., Kurian, G., Gruenwald, C., Beckmann, N., Celio, C., Eastep, J., & Agarwal, A. (2010). Graphite: A distributed parallel simulator for multicores. In HPCA - 16 2010 IEEE 16th International Symposium on High Performance Computer Architecture (pp. 1–12). IEEE. https://doi.org/10.1109/HPCA.2010.5416635
[15] Chen, J., Annavaram, M., & Dubois, M. (2009). SlackSim: A platform for parallel simulations of CMPs on CMPs. ACM SIGARCH Computer Architecture News, 37(2), 20–29. https://doi.org/10.1145/1555754.1555781
[16] Tan, Z., Qian, Z., Chen, X., Asanović, K., & Patterson, D. A. (2015). DIABLO: A warehouse-scale computer network simulator using FPGAs. In Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (pp. 331–344). Association for Computing Machinery. https://doi.org/10.1145/2694344.2694362